PQSC Key Features
- Control up to 100 qubits
- Synchronization of up to 18 HDAWGs, i.e., 144 output channels
- < 100 ns communication latency
- Customization through user access to FPGA Xilinx® UltraScale+™️ XCZU15EG-2I
- LabOne® control software (check compatibility) and APIs for LabVIEW, Python, C, MATLAB, .NET
PQSC Applications
- Superconducting qubits
- Semiconductor spin qubits
- Trapped ion qubits
PQSC Description
The PQSC comes with 18 ZSync ports to connect with Zurich Instruments HDAWG for qubit control and UHFQA for qubit readout. The scalable architecture supports setups with 100 and more accurately synchronized AWG channels and provides status monitoring to ensure quality and reliability of qubit tune-up routines. The ZSync links distribute the system clock to all instruments and synchronize all instruments to sub-nanosecond levels. Further they provide a bidirectional data interface to send qubit readout results to the PQSC for central processing, and to send trigger signals to the slave instruments to initiate synchronized actions. The ZSync links adhere to strict real-time behavior, all data transfers are predictable to single clock-cycle precision. This allows for implementation of rapid tune-up procedures, syndrome decoding and error correction routines. The LabOne control software provides a high-level interface to all instruments in the system and comes with APIs for LabVIEW, Python, C, MATLAB, .NET.
PQSC Specifications
| FPGA | |
| Type | Xilinx® UltraScale+™️ XCZU15EG-2I |
| System logic cells | 747k |
| CLB flip-flops | 682k |
| CLB LUTs | 341k |
| DSP slices | 3,528 |
| Block RAM | 26.2 Mb |
| UltraRAM | 31.5 Mb |
| CPUs and memory | |
| Application processor | Quad ARM® Cortex TM-A53 up to 1,333 MHz |
| Real-time processor | Dual ARM® Cortex TM-R5 up to 533 MHz |
| SDRAM | 4 GB DDR4 with ECC |
| Clock | |
| Input frequency | Auto-detect 10 MHz / 100 MHz |
| Input coupling | 50 Ω, SMA connector |
| Output frequency | Switchable 10 MHz / 100 MHz |
| Output amplitude | > 1 Vpp in 50 Ω |
| Connectivity and others | |
| Host connection | LAN / Ethernet, 1 Gbit/s USB 3.0 JTAG over USB 2.0 for Xilinx® ChipScope™️ access |
| device connection | 18 ZSync ports |
| ZSync communication bandwidth | Down-stream 200 MB/s Up-stream 100 MB/s |
| ZSync communication latency | < 100 ns |
| Trigger | 2 trigger inputs, 2 trigger outputs, 3.3 V TTL on SMA connector |
| Digital I/O | 32 bits, 3.3 V TTL, general purpose |